Job title
a senior verification engineer role is available in a leading technology company. The ideal candidate will have expertise in memory and storage solutions, with experience in developing verification infrastructure and environment to verify probe and burn dft testmodes functionality.
about the role
the successful candidate will work closely with a highly innovative and motivated design and verification team using state-of-the-art memory technologies to develop advanced dram and emerging memory products. Key responsibilities include developing verification infrastructure and environment to port-over the probe and burn dft patterns into the verification flow, providing verification support to the dram and emerging memory design engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
* main responsibilities:
* develop verification infrastructure and environment to verify probe and burn dft testmodes functionality.
* develop verification infrastructure and environment to port-over the probe and burn dft patterns into the verification flow.
* provide verification support to the dram and emerging memory design engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
* develop system-verilog testbench infrastructure (e.g. uvm/non-uvm and constrained random verification methodology).
* responsible for test plan execution, running regressions, code and functional coverage closure.
requirements
to be considered for this role, you should possess a deep understanding of cmos and dram circuit design and operation, familiarity with system-verilog testbench/uvm/constrained random verification methodology, good understanding of asic design flow including rtl design, verification, logic synthesis, and timing analysis, and familiarity with the dram dft flow and dft verification.
* required skills and qualifications:
* bs in electrical engineering, computer engineering or equivalent with at least 3-7 years of industry experience.
* deep understanding of cmos and dram circuit design and operation.
* familiarity with systemverilog testbench/uvm/constrained random verification methodology.
* good understanding of asic design flow including rtl design, verification, logic synthesis, and timing analysis.
* familiarity with the dram dft flow and dft verification.
benefits
this role offers a range of benefits, including a competitive salary, comprehensive health insurance, retirement plan, and paid time off. Additionally, you will have access to cutting-edge technology and tools, opportunities for professional development, and a collaborative and dynamic work environment.
* why work with us:
* we are a leading technology company with a rich portfolio of high-performance dram, nand, and nor memory and storage products.
* we are committed to innovation and excellence, with a relentless focus on our customers and manufacturing and operational excellence.
* we offer a collaborative and dynamic work environment, with opportunities for professional development and growth.
other information
please note that this role does not encompass the following responsibilities: finalization of sales agreements or the execution of sales contracts is prohibited, the role also does not carry the authority to make definitive decisions regarding contracts, be it their conclusion or termination, furthermore, the role is not designed to involve participation in pricing negotiations or the authorization of contracts.