We are seeking an experienced layout engineer to join our team. The successful candidate will be responsible for designing and developing ip layouts used in dram chips.key responsibilities:design and development of ip layouts used in dram chipsperform layout verification, quality check, and documentationresponsible for on-time delivery of block-level layouts with acceptable qualityguide and lead junior team members in their execution of sub-block level layouts and review their workplan and document layout, presenting material for global teams to reviewoptimally connect with engineering teams in various locations to ensure the success of the layout projectrequirements:6+ years of experience in layout designs in advanced cmos processable to perform ip layout development and physical verification activities for complex designs as per provided specificationsexpertise in layout area and routing optimization, design rules, yield, and reliability issuesgood understanding of layout fundamentals, including electromigration, latch-up, coupling, crosstalk, ir-drop, parasitic analysis, matching, shielding, etc.adequate knowledge of schematics, interface with circuit designer, and cad teamunderstanding of layout effects on circuits such as speed, capacitance, power, and areaexperience with cadence tools, including virtuoso schematic editor, virtuoso layout l, xl, and verification tools like mentor calibreproficient in device matching, parasitic analysis, electron migration, and isolation techniquesknowledge of skill coding and layout automation is a plus