Job details
this position requires candidates to upload an english resume. The role focuses on functional logic verification of an integrated soc to ensure the design meets specifications.
Responsibilities
perform functional logic verification of an integrated soc.
Define, develop, and implement scalable verification plans, test benches, and verification environments.
Execute verification plans and run emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.
Replicate, root‑cause, and debug issues in the pre‑silicon environment.
Find and implement corrective measures to resolve failing tests.
Collaborate and communicate with soc architects, microarchitects, full‑chip architects, rtl developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Document test plans and drive technical reviews of plans and proofs with design and architecture teams.
Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintain and improve existing functional verification infrastructure and methodology.
Absorb learning from postsilicon to update test plans for missing coverages and propagate improvements to future products.
Behavioral traits
collaborate within cross‑functional teams to resolve complex technical challenges.
Demonstrate analytical and problem‑solving skills with attention to detail.
Communicate technical concepts effectively to diverse audiences.
Show very good logical thinking, ability to prioritize work, and multi‑tasking.
Minimum qualifications
bachelor's degree in electrical engineering, computer engineering, computer science or a related field.
6+ months of experience in industry‑standard verification methodologies such as uvm or systemverilog or digital design.
Advanced english level.
Unrestricted, permanent right to work in mexico (no visa or immigration sponsorship).
Preferred qualifications
3+ years experience in systemverilog and uvm.
2+ years in:
python for test automation.
Simulation tools (vcs, xcelium, questa).
Arm‑based soc or equivalent architectures.
Pre‑silicon verification.
Memory subsystems, cache coherency, and power management.
Amba protocols (axi, ahb, apb) and interconnects.
Proficiency in c/c++ and scripting (perl, tcl, shell).
Formal verification tools and coverage analysis.
Constrained random and assertion‑based verification.
Linux/unix and version control (git, perforce).
Regression testing and ci/cd pipelines.
Security verification methodologies.
Experience with pre‑silicon functional verification, including planning, debug, testbench design, upf and coverage closure.
Job type
college grad
shift
shift 1 (mexico)
primary location
mexico, guadalajara
eeo statement
all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of trust
n/a
work model for this role
this role will require an on‑site presence.
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