Developers of high-quality pre-silicon functional validation tests verify that systems meet design requirements.
an engineer with expertise in rtl validation develops test plans and runs system simulation models to identify corrective measures for failing rtl tests.
the process involves analyzing results to modify testing procedures.
* a senior validation engineer independently leads the development and execution of pre-si validation for various ip, sub-system, and soc levels.
* this includes creating test plans, designing test bench architectures, and defining test methodologies. Engineers are also responsible for scheduling their tasks and managing junior engineers.
* leadership skills are essential for guiding junior engineers and developing technical proposals to support implementation.
* collaboration is key when working with architecture, design, soc validation, system validation, and firmware/software teams to resolve platform-level issues.
* participating in the development of architecture specifications for logic/val components is crucial.
key qualifications:
* superb communication and interpersonal skills are a must.
* excellent english communication skills are required.
* strong technical leadership skills are necessary.
* bachelor's in electronics engineering or related fields are preferred.
* at least 8 years of experience in ip/ss/soc pre-si validation with expertise in system verilog and uvm/ovm concepts are required.
* advanced english language proficiency is necessary.
* familiarity with asic development is beneficial.