The physical design engineer drives integration of analog and mixed signal ips and highspeed interfaces into subsystems or analog components and partners with package and platform teams on analog integration. Supports pathfinding studies in silicon development and relays feedback to silicon and packaging team on analog integration and tradeoffs. Guides the integration process from specification documentation to silicon tapeout and provides debugging support for analog functionality related debugs in the product. Possesses expertise in design verification flows, packaging effects, and integration flows to resolve integration challenges involved in mixed signal designs and deliver optimum performance of the overall circuit. Works closely with analog ip, soc architecture, soc design, package, and platform design functions to meet the analog specification for the product.
*qualifications*:
minimum qualifications:
- possess a bachelor's degree in electrical engineering or other stem fields.
- 4+ years of experience in the following:
- experience in floor planning (preferably in complex mixed-signal blocks involving multiple analog blocks)
- experience in debug of layout vs schematic (lvs), design rule checks (drc) and other layout verification flows.
- experience in one or more of the follow industry standard tools (i.e. Fusion compiler, primetime, conformal etc.)
- experience in one or more of the following scripting languages (eg. Tcl, perl, python etc.)
preferred qualifications:
- master's degree in stem.
- 6+ years of experience in physical design.
- synthesis and pnr flows on designs with greater than 500k instances.
*inside this business group*:
in the design engineering group (deg), we take pride in developing the best-in-class socs, cores, and ips that power intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of moore's law and groundbreaking innovations. Deg is intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all intel products, deg leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
*posting statement*:
all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
*benefits*:
we offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here.
*working model*:
this role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned intel site and off-site. *in certain circumstances the work model may change to accommodate business needs.*
jobtype
hybrid