Job description: this position requires candidates to upload an english resume (multiple versions are acceptable but an english version is required for consideration). Performs functional logic verification of an integrated soc to ensure design meets specifications. Defines and develops scalable, reusable block, subsystem, and soc verification plans, test benches, and verification environments to achieve required coverage and align with microarchitecture specifications. Executes verification plans, runs emulation and system simulation models to verify design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Implements corrective measures to resolve failing tests. Collaborates with soc architects, microarchitects, rtl developers, postsilicon, and physical design teams to improve verification of complex architectural features. Documents test plans and leads technical reviews with design and architecture teams. Incorporates security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Translates learning from postsilicon validation to update test plans for missing coverage and propagates to future products. Behavioral traits: collaborating within cross‑functional teams to resolve complex technical challenges analytical and problem‑solving skills with attention to detail communicating technical concepts effectively to diverse audiences strong logical thinking, prioritisation, and multitasking qualifications: minimum qualifications are required to be considered for this position. Preferred qualifications are additional and considered a plus factor. Bachelor's degree in electrical engineering, computer engineering, computer science or related field 5 years of industry‑standard experience or master’s degree with 4 years of experience 4 years of experience in: hardware description languages such as verilog or vhdl and verification tools like uvm or systemverilog or relevant silicon validation experience simulation or emulation tools, debugging scripts, and functional coverage analysis advance english level must have unrestricted, permanent right to work in mexico (no visa sponsorship). Preferred qualifications: advanced academic or professional experience contributing to complex cpu or soc design projects a passion for innovation and a drive to contribute to industry‑leading solutions 4 years systemverilog and uvm experience 4 years python for test automation proficiency in c/c++ and scripting (perl, tcl, shell) 2 years with simulation tools (vcs, xcelium, questa) formal verification tools and coverage analysis constrained random and assertion‑based verification 3 years arm‑based soc or equivalent architectures amba protocols (axi, ahb, apb) and interconnects memory subsystems, cache coherency, power management high‑speed interfaces (pcie, ddr, usb, ethernet) 3 years pre‑silicon verification experience linux/unix and version control (git, perforce) regression testing and ci/cd pipelines security verification methodologies experience in pre‑silicon functional verification, including planning, debug, testbench design, upf and coverage closure take the next step in advancing your career by applying your expertise to intel's groundbreaking server products. Shape the future of computing and make a lasting impact on the technology landscape. Job type: experienced hire shift: shift 1 (mexico) primary location: mexico, guadalajara posting statement: all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance. Position of trust: n/a work model for this role: this role will require an on‑site presence. J-18808-ljbffr