Delivers signal integrity solutions for large, complex highspeed platforms, boards, and packages.
- develops a viable space for all interconnects including 2d and 3d models extracts of electrical structures for the entire die-to-die interconnect.
- defines signal integrity rules, reviews implementation, documents characterization and measurement reports, and improves and optimizes design margins.
- applies knowledge of signal integrity design and tradeoffs to perform simulations of interconnect and guide package and platform physical implementation, and designs and characterizes test structures to correlate simulations and measurements for interconnects using intricate highspeed equipment and debugs challenges.
- develops electrical specifications and new industry standard interconnect specifications to guide consortiums for next generation interfaces.
- documents and provides implementation guidelines to the end customers as part of the platform design guide.
- collaborates with ip design teams and silicon integration teams to ensure the ip and soc designs maximize the platform level solution space to meet targeted product landing zone requirements and minimize quality degradation (e.g., attenuation, crosstalk, jitter, power noise) and cost.
*qualifications*:* minimum qualifications,*
you must possess the below minimum qualifications to be initially considered for this position:
- intermediate english level.
- must have unrestricted - permanent right to work in mexico.
*preferred qualifications*,
- signal integrity experience supporting highspeed differential signals and memory interfaces such as pcie ethernet ddr.
- fundamental knowledge of transmission line theory and highspeed printed circuit boards pcb design.
- experience with eda tools mentor graphics cadence etc.
- experience with simulation tools matlab, hspice, and ads.
- knowledge of intel architecture.
- design of experiments (doe) and statistical knowledge and experience would be an added advantage.
- transmission line modeling using field solvers ansoft 2d hfss, q3d, and cst electromagnetic simulator.
- lab equipment such as tdr vna digital oscilloscopes and logic analyzers.
- experience with silicon device modeling methods such as ibisami or verilog apcb layout process and methodology.
- experience using scripting languages e.g. Python, perl, etc.
- board-level system architecture basic silicon design io structures and topologies.
Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences.
*inside this business group*:
the data platforms engineering and architecture (dpea) group invents, designs & builds the world's most critical computing platforms which fuel intel's most important business and solve the world's most fundamental problems. Dpea enables that data center which is the underpinning for every data-driven service, from artificial intelligence to 5g to high-performance computing, and dcg delivers the products and technologies—spanning software, processors, storage, i/o, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
*posting statement*:
all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
*benefits*:
we offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our amazing benefits here.
*working model*:
this role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned intel site and off-site. *in certain circumstances the work model may change to accommodate business needs.*
jobtype
hybrid