A leading technology company is seeking a hands-on soc design verification engineer in guadalajara, mexico. The role involves driving verification of complex soc/ip blocks, from planning to execution. You will develop uvm testbench environments and collaborate cross-functionally to deliver high-quality silicon. Ideal candidates have a degree in electrical engineering, at least 5 years of experience in design verification, and strong skills in uvm/systemverilog, along with proficiency in english.#j-18808-ljbffr