A leading technology company is seeking a hands-on soc design verification engineer to drive verification for complex soc/ip blocks in guadalajara, mexico. This role includes developing uvm testbenches, collaborating with engineering teams, and ensuring coverage closure. The ideal candidate will have 5 years of experience in design verification and expertise in uvm/systemverilog, with a focus on delivering high-quality silicon on schedule. The position requires on-site presence and offers an exciting opportunity to contribute to cutting-edge technology. J-18808-ljbffr