Electrical validation expert
this role is crucial in defining the electrical validation strategy for memory io interfaces to achieve optimized performance and meet production goals. As an electrical validation engineer, you will be responsible for validating circuit analog performance, ensuring electrical signal integrity compliance to industry standards, and system-level margin for stable operation and production target prediction.
the ideal candidate will possess strong analytical and problem-solving skills, with the ability to conduct multidisciplinary research in memory io and mixed-signal architectures. You will develop procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation. Additionally, you will analyze internal and external customer returns to improve yields and drive test escape closure.
* main responsibilities:
* defines electrical validation strategy for memory io interfaces to achieve optimized electrical performance and meet product production goals.
* validates circuit analog performance, electrical signal integrity compliance to industry standard specifications, and system level margin for stable operation and production target prediction.
* conducts and participates in multidisciplinary research in the design, development, testing, validation, and utilization of memory io and mixed signal architectures inclusive of industry standard datacom applications and custom intel interfaces.
* develops procedures, analysis, and designs for validation, validation infrastructure, and systems margin validation.
* analyzes internal and external customer returns with emphasis on improving yields and driving test escape closure.
* applies and uses independent evaluation to select components and equipment based on analysis of specifications, performance, and reliability.
* performs debug to identify root causes and resolve all functional and triage failures for electrical issues.
* tests interactions between various electrical design features using validation infrastructure.
* applies understanding of dft and dfm to collaborate with architecture, design, and presilicon verification teams to ensure capability to validate and test io architecture implementations.
* prepares validation specifications, evaluates ip, and generates test reports.