We are seeking an advanced cmos process engineer to join our team. As a key member of our dram and emerging memory group, you will be responsible for designing and developing ip layouts used in dram chips.key responsibilities:design and development of ip layouts used in dram chips.perform layout verification like lvs/drc/em, quality check and documentation.on-time delivery of block-level layouts with acceptable quality.guide and lead junior team-members in their execution of sub-block level layouts & review their work.plan and document your layout, presenting material for global teams to reviewrequirements:6+ years of experience in layout designs in advanced cmos process.perform ip layout development and physical verification activities for complex designs as per provided specifications.expertise in layout area and routing optimization, design rules, yield and reliability issues.good understanding of layout fundamentals i.e. Electro-migration, latch-up, coupling, crosstalk, ir-drop, parasitic analysis, matching, shielding, etc.adequate knowledge of schematics, interface with circuit designer and cad team.understanding layout effects on the circuit such as speed, capacitance, power and area etc.experience with cadence tools including virtuoso schematic editor virtuoso layout l, xl & verification tools like mentor calibre- proficient in device matching, parasitic analysis, electron migration, and isolation techniques.skill coding and layout automation knowledge would be plus.education:be/btech or mtech in electronic/vlsi engineering or equivalent; we will also consider exceptionally talented diploma holders in electronic or vlsi engineering.