Lead efforts to develop and refine design rules, requirements, and test structures for all dram generations. Manage test structure evaluation to support next-gen device development and quantify process margins. Define sub-milestones within layout schedules and ensure timely execution across teams. Address process window vs. die size issues arising from database layout techniques. Collaborate with design, product engineering, process integration, business units, and quality teams to optimize ppac (performance, power, area, cost). Ensure robust design rule checks (drc) and appropriate responses to deviations. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across process integration, product engineering, design, and advanced mask teams. Improve documentation of r&d activities for design rule improvement ability to define and implement design rules within apr workflows to enhance layout efficiency and manufacturability.