We are seeking a highly skilled design verification engineer. The ideal candidate will have a background in working with companies that develop soc.
responsibilities:
* develop and execute verification plans for complex digital designs.
* create and maintain verification environments using industry-standard tools and methodologies.
* implement and debug test-benches and simulation environments.
* perform thorough verification of rtl designs, identifying and resolving any discrepancies.
* collaborate closely with design engineers to ensure comprehensive coverage and effective debugging.
* work with cross-functional teams to integrate verification efforts with overall design and development processes.
* participate in code and design reviews to ensure the highest quality standards.
* document verification plans, processes, and results, providing clear communication to stakeholders.
requirements:
* bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
* hands-on experience with verification tools such as uvm, systemverilog, and related eda tools.
* background in working with soc development companies is highly preferred.
* strong understanding of digital design principles and verification methodologies.
* excellent problem-solving skills and attention to detail.
* ability to work effectively in a collaborative team environment.
* strong communication skills, both verbal and written.