*qualifications.
*:
- master's degree or higher in electrical engineering.
- expertise in static timing analysis.
- strong coding skills in languages such as python, tcl, perl.
- strong methodology development background.
- strong analysis and communication skills.
*helpful experience.
*:
- familiarity with ansys redhawk/rhsc and pdn concepts.
- good insight in designing flows and software structure.
- familiarity with place and route tools and concepts.
- familiarity with post-silicon concepts, such as atpg vectors and test, silicon debug, defect and parametric limited yield.
- familiarity with hspice and transistor-level behavior.