Senior dram design layout engineer job description
at a leading technology firm, we are revolutionizing the way the world utilizes information to enrich life.
we seek a highly skilled senior dram design layout engineer to join our team in mexico. The ideal candidate will have 10+ years of experience in analog layout designs in sophisticated cmos processes and expertise in multiple ip layout library developments.
the successful candidate will be responsible for designing and developing analog layouts used in dram chips, performing layout verification, quality checks, and documentation. They will also lead junior team members, plan and document layouts, and contribute to effective project management and technical innovation.
key responsibilities:
* designing and developing analog layouts used in dram chips
* performing layout verification, quality checks, and documentation
* leading junior team members in their execution of sub-block-level layouts and reviewing their work
* contributing to effective project management and technical innovation
requirements:
* 10+ years of experience in analog layout designs in sophisticated cmos processes
* expertise in multiple ip layout library developments
* knowledge of dram chip architecture
* ability to perform ip layout development and physical verification activities for complex designs as per provided specifications
* experience with cadence tools including virtuoso schematic editor, virtuoso layout l, xl & verification tools like mentor calibre
* proficiency in device matching, parasitic analysis, electron migration, and isolation techniques