Job title: senior design verification engineer
we are seeking a talented and experienced senior design verification engineer to join our innovative team. In this role, you will be responsible for designing and verifying high-density memory chips with complex functionality, ultra-high speed, and advanced low power technology.
key responsibilities:
* evaluating design at chip or block level for functionality and providing solutions.
* collaborating with global design teams using verification tools and techniques, providing status updates.
* developing digital/analog mix-signal verification methodologies for advanced dram products and designing verification environments.
requirements:
* experience with systemverilog assertion (sva).
* bsc or msc in electrical or computer engineering with 6+ years of industry experience.
* experience in mixed-signal verification.
* familiarity with simulation tools like hspice, verilog hdl, finesim.
* knowledge of verification languages (systemverilog, uvm) and scripting languages (python, perl).
preferred qualifications: