Memory controller design engineer
in this position, you will be working with a global soc structural design team focused on the development of memory controllers for the optane family, where you will be contributing to the physical implementation of different mixed signal blocks from rtl to gds.
key responsibilities:
* block level floor planning, logic synthesis, formal equivalence verification (fev), auto place and route (apr), static timing analysis, physical verification, such as layout vs schematic (lvs), design rules checks (drc), electrical rule checks (erc), and design for manufacturability checks (dfm).
qualifications and skills:
* familiarity with any of the following fields:
* logic design synthesis.
* automatic place and route.
* performance verification including static and power analysis.
* layout verification (lvs, drc, and erc).
* scripting in tcl, perl, and python.
preferred qualifications:
* 3-6 months of experience in all qualifications listed above.
* experience with hardware description language, such as verilog and system verilog.
* computer architecture and logic design fundamentals.
* design fundamentals for low power and high speed circuits.
inside our group:
the data center & artificial intelligence group is at the heart of intel's transformation from a pc company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5g to high-performance computing, and our group delivers the products and technologies—spanning software, processors, storage, i/o, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
work model for this role:
this role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned location and off-site.