Job details
job description: this position requires candidates to upload a resume in english; you are welcome to upload multiple versions of your resume if you prefer but an english version of your resume will be required to be considered for this position.
Key responsibilities
defines, develops, and performs functional validation for integrated socs, focusing on validation of ip integration, interaction between ips, and system level features.
Applies various hardware and software level tools and techniques to ensure validation coverage and that performance, power, and area goals are met.
Reviews proposed design changes to assess impact on validation plans, tasks, and timelines.
Develops soc validation methodologies, validation test plans, executes validation plans, and collaborates with other engineers for design optimization, troubleshooting, and failure analysis.
Performs silicon debug to identify root causes and resolves all functional and triage failures for soc issues.
Tests interactions between various soc features using validation infrastructure.
Develops post silicon validation infrastructure (e.g., performance monitors, behavioral checkers, state space coverage) and test environment used in validation testing.
Publishes soc validation reports summarizing all validation activities performed, reviews results, and communicates to relevant teams.
Works with architecture, design, verification, board, platform, and manufacturing teams to maintain and improve debug, validation test strategy, methodologies, and processes for soc interfaces and to meet desired product specifications.
Develops content to create or increase specific ip interactions using a variety of tools and techniques (including patching techniques using microcode, firmware, or custom os builds).
Engages in all phases of the product life cycle and develops and validates content, infrastructure, and bug hunts in multiple environments (e.g., simulation, emulation, fpgas) to ensure silicon readiness.
This role requires regular onsite presence to fulfill essential job responsibilities.
Qualifications
minimum qualifications
bachelor's or master's degree in electrical engineering, computer engineering, computer science, or related field.
5+ years of total experience including experience in the following areas:
working/developing test plans
developing in a linux/unix environment.
Object‑oriented programming in c, c++, c#, perl and/or python software.
Hardware, system bring‑up, and/or silicon power‑on.
Advanced english level.
Must have unrestricted, permanent right to work in mexico (this role is not eligible for visa or immigration sponsorship).
Preferred qualifications
master's degree in electrical engineering, computer engineering, computer science, or related field.
7+ years of experience with one or more of the following:
hardware/rtl development or debug experience, rtl debug, review verilog code and correlate with waveform captures
developing test automation frameworks
debugging or developing fpga/emulation models
firmware/software debug of large c/c++ applications, provide fixes, github knowledge
experience with design and deriving testing for system clock/system reset flows.
Pcie protocol and/or pcie interfaces testing experience.
Lab equipment (logic analyzers, oscilloscopes, protocol analyzers).
Job type
experienced hire
shift
shift 1 (mexico)
location
mexico, guadalajara
work model for this role
this role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned intel site and off‑site.
Posting statement
all qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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