We are looking for a highly motivated sram mask layout designer to join our custom memory design team.
this entry-level position offers an opportunity to work on cutting‐edge semiconductor technologies and gain hands‐on experience in physical layout design for sram and other memory circuits.
responsibilities
assist in creating physical layouts for sram and custom memory blocks using industry‐standard cad tools (e.g., cadence virtuoso).
perform layout verification, including drc (design rule check), lvs (layout vs. Schematic), and erc.
collaborate with circuit designers to ensure layout meets performance, reliability, and manufacturability requirements.
maintain layout database using design management software.
engage with the engineering design team to understand design concepts, constraints, and milestones.
concisely and accurately report design status to the layout and engineering team; track schedules.
proactively and independently solve design and pdk issues; clearly communicate solutions to the layout and engineering team.
work closely with circuit designers and mask layout designers across integral sites (u.s., taiwan, india).
demonstrate effective communication and teamwork; work efficiently as part of an international team.
minimum qualifications
associate's degree or certificate in computer science, mathematics, electrical engineering, or related field.
basic understanding of cmos technology and ic design principles.
strong attention to detail and ability to work in a team environment.
preferred qualifications
bachelor's degree in computer science, engineering, or related field.
understanding of parasitic effects and reliability considerations.
familiarity with scripting languages (skill, python) for layout automation.
knowledge of advanced process nodes (e.g., finfet, gaa) is a plus.
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