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nxp’s high performance mixed signal technologies for automotive applications create new ways to make cars cleaner, safer, more comfortable, and more fun. Nxp’s advanced automotive analog (aa) business unit’s mission is to provide a broad portfolio of differentiated analog, mixed-signal, wireless, and energy management solutions that enable our customers to realize compelling green, safe, connected, and secure products for the automotive market.
in the apn business unit, the advanced power systems (aps) segment drives the business of nxp’s leading power management products for automotive, industrial, and iot markets. Together with a worldwide design team, we develop application specific standard products which integrate high performance analog functions as well as digital logic.
for our fast-growing product line we are currently looking for a candidate for a senior/lead digital verification position to drive the digital functional verification of our mixed-signal circuit designs in automotive platforms, iot/consumer and/or industrial platforms. This candidate will work closely with nxp verification architect/lead and will drive the local team.
the candidate will have excellent communication skills and proven ability to collaborate across organizational and geographical boundaries.
successful applicants will be responsible for:
studying the specification of the device under test.
* defining the test specification in closed collaboration with design leaders, verification architect/lead and product definers.
* defining the digital verification planning to reach 100% functional coverage prior tapeout.
* developing and/or running the uvm simulation environment (drivers, monitors, checkers and assertions) and bridge it with mixed signal verification.
* being the team’s expert in sv, sva, uvm and metrics driven verification.
* mentoring verification engineers on sv, sva, uvm and other latest verification methodologies.
* developing and/or running formal verification environment.
* developing and/or running digital and top-level simulations according to the verification plan
* preparing and holding design verification reviews.
* creating and maintaining regression test suites.
* reporting bugs, proposing solutions and following their resolution.
* leading the digital verification team on ic development projects.
the candidate will work closely with analog and digital designers as well as test and validation engineers to support both pre-silicon verification and post-silicon validation. This is an opportunity for a skilled verification engineer to take the next step into technical leadership.
working in a strong technical biased environment, you will develop your competencies and will have the opportunity of evolving in both technical or project responsibilities.
if you have the passion for innovation, the desire to challenge yourself and want to put your creativity in enabling latest technologies in automotive, iot, industrial applications, this is the right opportunity to join the leader.
qualifications
required
* bs/ms in ee and 10+ years of hands-on experience on digital verification methodologies (metrics driven verification, formal)
* strong experience writing verification plans, creating test benches and automating regression test suites, preparing and presenting detailed verification reviews
* technical leadership skills to lead a worldwide team of dv engineers executing verification on an ic.
* ability to own, execute and deliver dv coverage closure on an ic.
* good understanding of digital rtl debug.
* working knowledge of state-of-the-art eda tools: cadence xcelium, cadence vmanager, cadence jaspergold.
* strong background in design and verification languages and methodologies (verilog, systemverilog, uvm, sva).
* experience in configuration database management (designsync, git, svn)
* solid scripting skills (python preferred or perl or tcl).
optional
* experience with mixed signal (analog, digital) verification methodologies
* experience developing behavioral models for analog ips (both wreal or sv rnm)
* understand and debug analog schematics
seniority level
* seniority level
mid-senior level
employment type
* employment type
full-time
job function
* industries
semiconductor manufacturing
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legal assistant - only cvs in english will be accepted
verification application engineer, principal
guadalajara, jalisco, mexico mx$11,000.00-mx$13,500.00 1 day ago
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