Senior verification engineer
this role is focused on the development and implementation of verification infrastructure and environments to support the creation of advanced memory products.
* develop verification environments and tools to verify probe and burn dft testmodes functionality.
* port-over probe and burn dft patterns into the verification flow, ensuring seamless integration with design engineering teams.
* provide expert-level verification support to design engineers by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
* design and develop systemverilog testbench infrastructure, leveraging uvm/non-uvm and constrained random verification methodology to drive innovation in memory product development.
* execute test plans, run regressions, and drive code and functional coverage closure to ensure high-quality memory products.
requirements:
* bs in electrical engineering, computer engineering, or equivalent with at least 3-7 years of industry experience.
* deep understanding of cmos and dram circuit design and operation, including familiarity with systemverilog testbench/uvm/constrained random verification methodology.
* good understanding of asic design flow, including rtl design, verification, logic synthesis, and timing analysis.
* familiarity with the dram dft flow and dft verification, with a strong focus on delivering high-quality results.
what we offer:
* rich portfolio of high-performance dram, nand, and nor memory and storage products through our micron and crucial brands.
* relentless focus on customers, technology leadership, and manufacturing and operational excellence drives innovation that fuels the data economy.