Job details:
job description:
you will be part of intel labs silicon design prototyping team working on the design of new and novel digital and analog circuits layout.
in this position, you will contribute to intel's chip-to-chip i/o research with a focus on practical applications for future products. Responsibilities include layout design of analog and mixed-signal chip designs, such as fet, cell, and block-level custom layouts, auto place and route algorithms, floor planning, and full chip assembly.
qualifications:
minimum qualifications required for initial consideration:
* pursuing a master's degree in electrical engineering or a related field (must remain an active student for at least 1 year).
* at least 1 year of experience developing scripts with python.
* at least 1 year of experience in digital or analog circuit layout.
* at least 1 year of experience using automatic place and route tools (icc, fusion compiler, virtuoso).
* intermediate to advanced english proficiency.
* unrestricted, permanent right to work in mexico.
preferred qualifications (additional to minimum requirements):
* pursuing a phd in electrical engineering or a related field.
* over 2 years of experience in analog circuit layout.
* over 2 years of experience in gui development using python.
these qualifications may be obtained through relevant industry experience, internships, schoolwork, classes, or research.
applicants accepting employment in mexico must provide personal identification information, including the mexican security number (nss), tax identification number (rfc), and curp.
additional details:
* job type: student / intern
* shift: shift 1 (mexico)
* primary location: mexico, guadalajara
* business group: intel labs, responsible for pioneering research and technology development.
* work model: hybrid, allowing a mix of on-site and off-site work, subject to change.
all qualified applicants will receive consideration without discrimination based on race, color, religion, sex, national origin, or other protected characteristics.
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