Verification engineer opportunity
we are innovating memory and storage solutions that accelerate information transformation into intelligence.
this role involves developing verification infrastructure and environment to verify probe and burn dft testmodes functionality, port-over the probe and burn dft patterns into the verification flow, and providing verification support to dram and emerging memory design engineering teams by simulating, analyzing, and debugging pre-silicon full-chip and block-level designs.
* develop systemverilog testbench infrastructure (e.g. Uvm/non-uvm and constrained random verification methodology)
* execute test plans, run regressions, code and functional coverage closure
the ideal candidate will have a bs in electrical engineering, computer engineering or equivalent with at least 3-7 years of industry experience, a deep understanding in cmos and dram circuit design and operation, familiarity with systemverilog testbench/uvm/constrained random verification methodology, and good knowledge of asic design flow including rtl design, verification, logic synthesis, and timing analysis.