Rtl design verification engineerrole overview:responsible for verifying rtl designs using systemverilog and uvm to ensure design correctness and functionality before chip fabrication.key responsibilities:develop test plans and uvm-based test suitesconduct ip, module, subsystem, and soc-level verificationperform testbench linting and formal assertion checksverify low-power features and create emulation and fpga prototypesskills required:strong proficiency in systemverilog and uvmexperience in formal verification and low-power design validationfamiliarity with emulation models and fpga prototypingability to develop scalable and reusable verification environments