Rtl design verification engineer
role overview:
responsible for verifying rtl designs using
systemverilog
and
uvm
to ensure design correctness and functionality before chip fabrication.
key responsibilities:
develop
test plans
and
uvm-based test suites
conduct
ip ,
module ,
subsystem, and
soc-level verification
perform
testbench linting
and
formal assertion checks
verify
low-power features
and create
emulation
and
fpga prototypes
skills required:
strong proficiency in
systemverilog
and
uvm
experience in
formal verification
and
low-power design validation
familiarity with
emulation models
and
fpga prototyping
ability to develop scalable and reusable verification environments