Overview
as a leading technology innovator, we push the boundaries of what's possible to enable next‑generation experiences and drive communication and data processing transformation to help create a smarter, connected future for all. As an asic engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document ip (block/soc) development for a variety of high performance, high quality, low power world‑class products. Engineers collaborate with cross‑functional groups to determine product execution path.
Digital asic team is actively seeking candidates for several physical design engineering positions in our soc and core design team. As a physical design engineer you will innovate, develop, and implement chips and cores using state‑of‑the‑art tools and technologies.
Responsibilities
you will be part of a team responsible for the complete physical design flow and deliveries of complex, high‑speed, low‑power designs such as gpu, camera and other mm, ddr, modem, audio. Tasks also involve the development and enablement of low‑power implementation methods, customized p&r to achieve area reduction, performance, and power goals. Additional responsibilities in this role involve good understanding of functional and test (dft) mode constraints for place and route, floorplanning, power planning, ir drop analysis, cell placement, multi‑mode & multi‑corner (mmmc) clock‑tree synthesis, routing, timing optimization and closure, rc extraction, signal integrity, cross‑talk noise and delay analysis, debugging timing violations for mmmc designs, implementing timing fixes and functional ecos, debugging and fixing physical violations, and formal verification. The individual also should have deep knowledge on scripting and software languages including python, perl/tcl, linux/unix shell and c. This individual will design, verify, and deliver complex physical design solutions from netlist and timing constraints to the final product.
Qualifications
bachelor's / masters degree in science, engineering, or related field
preferred qualifications
2+ years industry experience/coursework in the following areas:
physical design
place & route tool experience on cadence innovus and/or synopsys fusion compiler
timing closure experience in synopsys ptsi
formal verification experience
power domain analysis experience
physical verification experience
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